• David J. Lilja

    David Lilja photo

    Dr. Lilja received the Ph.D. and M.S. in Electrical Engineering from the University of Illinois at Urbana‐Champaign, and a B.S. in Computer Engineering from Iowa State University in Ames. He is currently the Louis John Schnell Professor of Electrical and Computer Engineering at the University of Minnesota in Minneapolis, where he also serves as the ECE department head, as a member of the graduate faculties in Computer Science and Scientific Computation, and as a Fellow of the Minnesota Supercomputer Institute. Previously, he worked at the Center for Supercomputing Research and Development at the University of Illinois, and as a development engineer at Tandem Computers Incorporated in Cupertino, California. He has chaired and served on the program committees of numerous conferences, and was a distinguished visitor of the IEEE Computer Society. He received a Fulbright Senior Scholar Award to visit the University of Western Australia in 2001, and was awarded a McKnight Land‐Grant Professorship by the Board of Regents of the University of Minnesota. He is internationally recognized for his research in computer architecture, parallel processing, computer systems performance analysis, high‐performance storage systems, and the interaction of computer architecture and circuits. His contributions have been recognized as a Fellow of both the Institute of Electrical and Electronics Engineers (IEEE) and the American Association for the Advancement of Science (AAAS). The following papers highlight some of his work in areas related to this proposal.


    1. A. Lyle, S. Patil, J. Harms, B. Glass, X. Yao, D. Lilja, and J.-P. Wang, “Magnetic tunnel junction logic architecture for realization of simultaneous computation and communication,” IEEE Trans. Magn. 47, 2970 (2011).
    2. A.Lyle, J. Harms, S. Patil, X. Yao, D. J. Lilja, and J.-P. Wang, “Direct communication between magnetic tunnel junctions for non-volatile logic fan-out architecture,” Appl. Phys. Lett. 97, 152504 (2010).
    3. S. Patil, A. Lyle, J. Harms, D. J. Lilja, and J.-P. Wang, “Spintronic logic gates for spintronic data using Magnetic Tunnel Junctions,” IEEE International Conference on Computer Design (ICCD), October, 2010.
    4. S. R. Patil, X. Yao, H. Meng, J.-P. Wang, and D. J. Lilja, “Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions,” ACM International Conference on Computing Frontiers, May, 2008.
    5. W. Qian, X. Li, M. D. Riedel, K. Bazargan, and David J. Lilja, “An architecture for fault-tolerant computation with stochastic logic,” IEEE Trans. Comput. 60, 93 (2011).
    6. W. Qian, C. Wang, P. Li, D. J. Lilja, K. Bazargan, and M. D. Riedel, “An efficient implementation of numerical integration using logical computation on stochastic bit streams,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November, 2012.
    7. P. Li, W. Qian, and D. J. Lilja, “A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic,” IEEE International Conference on Computer Design (ICCD), September, 2012.
     
     
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